In semiconductor device fabrication, back-end-of-line (BEOL) wafer processing generally involves creating various interconnecting metal layers that may be interconnected by vias. Wire bonding pads or pad interconnects are connected to the interconnects and are used to connect an integrated circuit (IC) to other ICs or electronic devices. Wire bonds are attached to the wire bonding pads.
However, we have observed that some traditional wire bond pad structures suffer from several disadvantages. For example, traditional wire bond pad structure experiences high shear stress due to coefficient thermal expansion (CTE) mismatch between the conductive bond pad and underlying dielectric layer. This causes the passivation layer disposed over the conductive bond pad to crack and delaminate from the dielectric layer. In addition, we have also found that traditional wire bond pad structures have high risk of low bump yield due to poor under bump metallization (UBM) gap fill and undesired bump residues appearing in the passivation layer, lowering the reliability of the wire bond pad structures.
From the foregoing discussion, it is desirable to provide reliable bond pad structures and methods of manufacturing the same.